Reference Map
Compute Supply Chain
What an AI accelerator is made of — and where The Grid can see supply-chain pressure. Every leading-edge accelerator shares the same upstream chokepoints: one foundry, one lithography supplier, one packaging bottleneck, three memory makers. Vendor substitution at the GPU level does not relieve constraints upstream of the fork. When a provider promises delivery, this is the chain that has to deliver it — the structural register behind every price and capacity claim The Grid records.
This map shows the dependency structure and marks honestly what we measure and what we cannot. The gaps are the finding — they show where the surprises come from.
3 instrumented·10 proxy·46 gap
Click any node for detail.
└─ ▶Logic Die (TSMC N4/N2)[proxy]TSMC the only foundry making 3nm/2nm at scale
├─ ▶Wafer Fab Process[proxy]
│ ├─ ▶Gallium / Germanium[gap]China ~80-98% of refined Ga/Ge
│ ├─ ▶Specialized Labour[gap]US shortfall up to 300K; overseas-fab ramps delayed by staffing
│ ├─ ▶EUV Lithography (ASML)[gap]ASML 100% of EUV (low- and high-NA)
│ ├─ ▶Silicon Wafers[gap]Shin-Etsu + SUMCO (Japan) >50% combined; top-5 ~85%
│ │ └─ ▶High-Purity Quartz (Spruce Pine)[gap]Spruce Pine, NC ~80% of world HPQ; Sibelco >90% of top-grade 4N8+
│ ├─ ▶Photoresist (EUV-grade)[gap]Japan-concentrated; JSR >22% share, owns Inpria/metal-oxide-resist leader
│ ├─ ▶Specialty Process Gases[gap]China ~14M m3/yr installed neon, +20% YoY
│ └─ ▶Photomask Blanks[gap]Duopoly Hoya + AGC for blanks; EUV pellicles even thinner-sourced
└─ ▶Foundry Capex & Fab Construction[proxy]TSMC dominant; ASML sole litho supplier
120d ──▸ GPU / AI Accelerator
├─ ▶Advanced Packaging (CoWoS)[gap]TSMC dominant; NVIDIA secured ~60% of 2026 CoWoS allocation
│ 180d ──▸ GPU / AI Accelerator
│ ├─ ▶ABF Substrate (Ajinomoto)[gap]Ajinomoto >95% of ABF film
│ ├─ ▶Silicon Interposer[gap]TSMC dominant; interposer capacity is a CoWoS sub-bottleneck
│ ├─ ▶Thermal Compression Bonding (TCB)[gap]Besi ~50%+ of advanced TCB equipment market
│ └─ ▶Test & Known-Good-Die (KGD)[gap]Advantest + Teradyne ~80% of advanced ATE
└─ ▶OSAT Overflow Packaging[gap]ASE + Amkor lead merchant OSAT advanced packaging
└─ ▶HBM Memory Stack[proxy]SK Hynix ~50-62%, Samsung ~25-40%, Micron ~5-20%
225d ──▸ GPU / AI Accelerator
└─ ▶Commodity DRAM (DDR5)[instrumented]Three-firm oligopoly (same as HBM)
90d ──▸ GPU / AI Accelerator
├─ ▶Grid-Operator Curtailment Regimes[gap]PJM first (largest US grid, 67M customers); other operators expected to follow
└─ ▶Datacenter Facility[gap]Top-5 DC operators + hyperscaler self-builds
180d ──▸ Compute (root)
├─ ▶Grid Interconnection & Power Delivery[proxy]Fragmented across regional grid operators; queue governance varies by jurisdiction
│ └─ ▶Large Power Transformers & Switchgear[gap]Global oligopoly; US domestic capacity severely short
├─ ▶Cooling Systems[gap]Vertiv + Schneider dominate traditional; CoolIT leads direct-to-chip liquid
│ └─ ▶Water Supply[gap]Municipal/regional water authorities; no market concentration
├─ ▶Power Generation & Procurement[gap]GE Vernova + Siemens Energy dominate heavy-frame gas turbines
└─ ▶Land, Permitting & Siting[gap]Fragmented; hyperscalers increasingly self-develop to bypass DC REIT queues
├─ ▶Networking & Interconnect[gap]NVIDIA dominant for AI-specific interconnect; Broadcom + Arista for Ethernet fabric
│ ├─ ▶High-Speed Connectors[gap]Amphenol + TE ~50%+ of high-speed datacenter connectors
│ ├─ ▶Fiber & Copper Cabling[gap]Corning dominant in fiber; connector market more fragmented
│ ├─ ▶Optical Transceivers (800G/1.6T)[gap]Coherent + Innolight ~50%+ of 800G; Chinese suppliers (Eoptolink) rising
│ │ └─ ▶Laser Chips & InP Wafers[gap]AXT + JX Nippon + InPact cover most InP wafer supply
│ └─ ▶Switch Silicon / NIC ASICs[gap]Broadcom ~70%+ of merchant Ethernet switch silicon
└─ ▶Optical Interconnect (3.2T / CPO Transition)[gap]
├─ ▶GPU / AI Accelerator[instrumented]NVIDIA dominant in merchant AI accelerators
│ └─ ▶Board & System Integration[gap]Supermicro dominant in AI GPU servers; Quanta/Foxconn for hyperscaler custom
│ ├─ ▶High-Bandwidth Interconnect (NVLink / PCIe)[gap]Astera Labs dominant in CXL/PCIe retimers; NVLink copper assemblies concentrated
│ └─ ▶Power Management (PMICs / VRMs)[gap]Monolithic Power Systems dominant for GPU VRMs; Renesas + Infineon for server power
├─ ▶China Domestic AI Silicon[gap]
└─ ▶Wafer-Scale Accelerator[gap]Single merchant vendor — wafer-scale is a one-company class today
├─ ▶Neocloud (GPU Cloud Pure-Play)[proxy]CoreWeave dominant among listed pure-plays by fleet scale
│ ├─ ▶CoreWeave (CRWV)[proxy]
│ ├─ ▶Nebius (NBIS)[proxy]
│ └─ ▶Financing & Credit Structure[gap]
├─ ▶Foundation Labs[gap]Top-5 labs consume ~60-70% of leading-edge training GPU-hours
│ ├─ ▶Frontier Inference[proxy]
│ │ └─ ▶Inference Software Efficiency[gap]
│ └─ ▶Training Compute[gap]
├─ ▶Hyperscalers / Clouds[gap]
│ ├─ ▶Cloud GPU-as-a-Service[instrumented]
│ ├─ ▶Datacenter Buildout Capex[proxy]
│ │ 1095d ──▸ Grid Interconnection & Power Delivery
│ └─ ▶Custom Silicon Programs[gap]
│ ├─ ▶Defense & Intelligence[gap]
│ └─ ▶National AI Programs[gap]
├─ ▶Agentic Workloads[gap]
│ 7d ──▸ Compute (root)
└─ ▶Robotics / Physical-AI Demand[gap]
What is bound, and by what
The longest stored lags
The map’s stored propagation edges, longest first — each lag is a stored, dated structural fact about how long an upstream condition takes to reach downstream capacity, never a prediction about when anything will happen.
| Lag | From → To | Relationship | The stored description |
|---|
| ~1095d | Datacenter Buildout Capex → Grid Interconnection & Power Delivery | propagates | Campus announcements propagate to the power-demand queue. July 2026 board: SoftBank up to EUR 75B / 5GW northern France (3.1GW phase 1); AirTrunk $21B / 3GW Maharashtra; Google $15… |
| ~225d | HBM Memory Stack → GPU / AI Accelerator | propagates | HBM share rotation propagates to accelerator BOM: SK hynix 62 / Micron 21 / Samsung 17 share; SK hynix HBM4 development complete (10 Gbps, mass production pending qualification, sl… |
| ~180d | Datacenter Facility → Compute (root) | propagates | Power/datacenter pipeline changes propagate to compute capacity (Chain 3: Power Infrastructure) |
| ~180d | Advanced Packaging (CoWoS) → GPU / AI Accelerator | propagates | Packaging utilization propagates to GPU availability/pricing (Chain 2: Packaging Constraint). Q2 2026 re-date: TSMC 2026 capex raised $52-56B to $60-64B explicitly for the 2nm ramp… |
| ~180d | Logic Die (TSMC N4/N2) → Wafer-Scale Accelerator | needs | Wafer-scale accelerator consumes full leading-edge wafers (TSMC) — it bypasses packaging and external HBM, not the foundry. Estimated lag ~180d (2 quarters), wafer-start to system … |
| ~120d | Foundry Capex & Fab Construction → GPU / AI Accelerator | propagates | Foundry revenue/capex signals propagate to GPU supply volume (Chain 4: TSMC Revenue Signal) |
| ~90d | Commodity DRAM (DDR5) → GPU / AI Accelerator | propagates | DRAM spot price propagates to GPU rental pricing via HBM cost stack (Chain 1: HBM Bottleneck) |
| ~7d | Agentic Workloads → Compute (root) | pulls | Agentic demand surges pull on compute supply (Chain 6: Demand Feedback) |
stored static_lag_days · dated structural record · no forecasting
Coverage and dependency structure from the Grid graph store (dependency-map Stages 1-4). All seven segments recursed to natural floor. Coverage tags: [instrumented]direct daily series · [proxy]adjacent stand-in · [gap] structure mapped, no live data.